Phase-locked-loops (PLLs) have been traditionally used in telecommunication products to generate and receive modulated signals. In addition, the use of phase-locked-loops has been extended to include advanced digital technologies. For example, microprocessors and microcontrollers commonly use phase-locked-loops to insure proper operation.
Phase locked loops can be used to provide a signal of fixed frequency. For modem digital components, these signals can be system clocks ranging in frequency from 10's to 100's of megahertz. It is well known that the use of devices having high frequency clocks generate electromagnetic interference (EMI). EMI is generated not only at the fixed clock rate, but also at the harmonics associated with the fixed clock rate. The resulting EMI can interfere with critical communication frequency transmission bands, including radio, television, and emergency broadcast channels. As a result of EMI, the received communication signals appear to be corrupted at the receiver end.
In order to assure operation of electronic devices does not compromise communication channels, the Federal Communications Commission, and its foreign counterparts, have mandated specific EMI transmission levels to which electronic systems are to be compliant.
One known method to reduce EMI transmission levels is the use of shielding applied at the system application level. For example, it is well known to use shielding in order to limit the EMI transmission in systems such as desktop computers. In addition, magnetic shielding devices have been applied to connector cables in order to filter EMI effects of transmitted signals. However, such system level EMI reducing techniques are not practical for all applications.
Another known technique to reduce the EMI effects of high frequency electronic components is to dither the frequency of the input clock. By dithering the clock frequency, the amount of peak energy EMI transmissions in a specific frequency band is reduced by spreading the peak energy over a larger bandwidth. While the total EMI energy remains unchanged, it is spread over a larger bandwidth, thereby reducing the effects of peak energy EMI at any specific frequency.
Clock dithering techniques in the prior art include the use of a dedicated PLL to generate a control voltage for a replica VCO which provides the clock output. The control voltage applied to the replica VCO reflects the control voltage necessary for generating a signal having a desired average frequency. For example, the desired output of the dedicated phase-locked-loop could be a control voltage capable of generating a 33 MHz signal. This control voltage, derived from the dedicated PLL to generate the desired average frequency, is provided to the replica voltage-controlled oscillator, which drives the system clock. In addition to the control voltage from the dedicated PLL, a periodically varying voltage signal, generally referred to as a modulating signal, is also provided to the replica VCO used to generate the system clock. By adding the received control voltage and the modulating signal, the replica VCO will produce a modulating, or dithered, clock output. For example, the 33 MHz clock may now be dithered by a range of +/-1 MHz. The amount of dithering selected is subject to the dynamic limitations of the electronics utilized.
The voltage-controlled oscillator associated with the dedicated phase-locked-loop is phase corrected by the voltage control signal previously described. Likewise, the voltage-controlled oscillator associated with the output driver portion of the prior art is also controlled by the previously described voltage control signal. However, any difference between the two voltage-controlled oscillators will result in a center frequency error on the output driver. This frequency error is not corrected by the phase-locked-loop. As a result, it is not possible to generate the desired centering frequency due to the uncompensated error associated with components of the output driver voltage-controlled oscillator. Secondly, the amount of frequency deviation achieved is not directly proportional to the center frequency due in part to the uncompensated error of the driver VCO and to the method of deriving the modulating signal.
Therefore, it would be desirable to identify a method and apparatus capable overcoming problems associated with the prior art FMPLLs.